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r ev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD5233 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 functional block diagram o 1 addr decode AD5233 sdi serial interface cs clk sdi sdo sdo pr wp rdy eemem control rdac1 register v dd 11 bytes user eemem digital 5 register digital output buffer o 2 eemem5 rdac1 w 1 b 1 a 1 v ss rdac2 register eemem2 eemem1 rdac3 register eemem3 rdac4 register eemem4 rdac2 w 2 b 2 a 2 rdac3 w 3 b 3 a 3 rdac4 w 4 b 4 a 4 2 gnd general description the AD5233 provides a nonvolatile memory, digitally controlled set of potentiometers 2 with 64-position resolution. these devices perform the same electronic adjustment function as a mechanical potentiometer. the AD5233s versatile programming via a stan- dard 3-wire serial interface allows sixteen modes of operation and adjustment including scratch pad programming, memory storing and retrieving, increment/decrement, log taper adjustment, wiper setting readback, and extra user defined eemem. in the scratchpad programming mode, a specific setting can be programmed directly to the rdac 2 register, which sets the resistance at terminals wCa and wCb. the rdac register can also be loaded with a value previously stored in the eemem 1 register. the value in the eemem can be changed or protected. when changes are made to the rdac register, the value of the new setting can be saved into the eemem. thereafter, such value will be transferred automatically to the rdac register during system power on, which is enabled by the internal preset strobe. eemem can also be retrieved through direct programming and external preset pin control. features nonvolatile memory 1 preset maintains wiper settings 4-channel independent programmable 64-position resolution full monotonic operation 10 k , 50 k , and 100 k terminal resistance permanent memory write protection wiper settings readback linear increment/decrement log taper increment/decrement push button increment/decrement compatible spi compatible serial interface with readback function 3 v to 5 v single supply or 2.5 v dual supply 11 bytes user nonvolatile memory for constant storage 100-year typical data retention t a = 55 c applications mechanical potentiometer replacement instrumentation: gain, offset adjustment programmable voltage to current conversion programmable filters, delays, time constants line impedance matching power supply adjustment the linear step increment and decrement commands allows the setting in the rdac register to be moved up or down, one step at a time. for logarithmic changes in wiper setting, a left/right bit shift command adjusts the level in 6 db steps. code ?decimal 100 75 0 063 16 32 48 50 25 r wb r wa r wa (d), r wb (d), ?% of full-scale r ab figure 1. r wa (d) and r wb (d) vs. decimal code the AD5233 is available in a thin tssop-24 package. all parts are guaranteed to operate over the extended industrial temperature range of C40 c to +85 c. nonvolatile memory, quad 64-position potentiometers notes 1 the terms nonvolatile memory and eemem are used interchangeably. 2 the terms digital potentiometer and rdac are used interchangeably. * patent pending
rev. 0 C2C AD5233?pecifications electrical characteristics?0 k , 50 k , and 100 k versions (v dd = 3 v 10%, or 5 v 10%, and v ss = 0 v, v a = v dd , v b = 0 v, ?0 c < t a < +85 c unless otherwise noted.) parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resistor differential nonlinearity 2 r-dnl r wb, v a = nc, monotonic C0.5 0.1 +0.5 lsb resistor integral nonlinearity 2 r-inl r wb, v a = nc C0.5 0.1 +0.5 lsb nominal resistor tolerance r wb d = 3f h C40 +20 % resistance temperature coefficient r ab / ? t 600 ppm/ c wiper resistance r w i w = 100 a 15 100 ? code = half-scale dc characteristics potentiometer divider mode resolution n 6 bits differential nonlinearity 3 dnl monotonic C0.5 0.1 +0.5 lsb integral nonlinearity 3 inl C0.5 0.1 +0.5 lsb voltage divider temperature coefficient v w / t code = half-scale 15 ppm/ c full-scale error v wfse code = full-scale C1.5 0 %fs zero-scale error v wzse code = zero-scale 0 +1.5 %fs resistor terminals terminal voltage range 4 v a, b, w v ss v dd v capacitance 5 a, b c a, b f = 1 mhz, measured to gnd, 35 pf code = half-scale capacitance 5 wc w f = 1 mhz, measured to gnd, 35 pf code = half-scale common-mode leakage current 5, 6 i cm v w = v dd /2 0.015 1 a digital inputs & outputs input logic high v ih with respect to gnd, v dd = 5 v 2.4 v input logic low v il with respect to gnd, v dd = 5 v 0.8 v input logic high v ih with respect to gnd, v dd = 3 v 2.1 v input logic low v il with respect to gnd, v dd = 3 v 0.6 v input logic high v ih with respect to gnd, v dd = +2.5 v, 2.0 v v ss = C2.5 v input logic low v il with respect to gnd, v dd = +2.5 v, 0.5 v v ss = C2.5 v output logic high (sdo, rdy) v oh r pull-up = 2.2 k ? to 5 v 4.9 v output logic low v ol i ol = 1.6 ma, v logic = 5 v 0.4 v input current i il v in = 0 v or v dd 2.5 a input capacitance 5 c il 4pf output current 5 i o1 , i o2 v dd = 5 v, v ss = 0 v, t a = 25 o c, 50 ma sourcing only v dd = 2.5 v, v ss = 0 v, t a = 25 o c, 7 ma sourcing only power supplies single-supply power range v dd v ss = 0 v 2.7 5.5 v dual-supply power range v dd /v ss 2.25 2.75 v positive supply current i dd v ih = v dd or v il = gnd 3.5 10 a programming mode current i dd(pg) v ih = v dd or v il = gnd 40 ma read mode current 7 i dd(xfr) v ih = v dd or v il = gnd 0.3 3 9 ma negative supply current i ss v ih = v dd or v il = gnd, v dd = +2.5 v, v ss = C2.5 v v a = +2.5 v, v b = C2.5 v 0.55 10 a power dissipation 8 p diss v ih = v dd or v il = gnd 0.018 0.05 mw power supply sensitivity 5 p ss ? v dd = 5 v 10% 0.002 0.01 %/%
rev. 0 C3C AD5233 parameter symbol conditions min typ 1 max unit dynamic characteristics 5, 9 bandwidth bw C3 db, r ab = 10 k ? /50 k ? /100 k ? 630/130/66 khz total harmonic distortion thd w v a = 1 vrms, v b = 0 v, f = 1 khz, r ab = 10 k ? 0.04 % total harmonic distortion thd w v a = 1 vrms, v b = 0 v, f = 1 khz, r ab = 50 k ? , 0.015 % 100 k ? v w settling time t s v a = v dd , v b = 0 v, v w = 0.50% error band, code 000 h to 200 h for r ab = 10 k ? /50 k ? /100 k ? 0.6/2.2/3.8 s resistor noise voltage e n_wb r wb = 5 k ? , f = 1 khz 9 nv/ hz crosstalk (c w1 /c w2 )c t v a = v dd , v b = 0 v, measure v w with adjacent rdac making full-scale code change C1 nvCs analog crosstalk (c w1 /c w2 )c ta v dd = v a1 = +2.5 v, v ss = v b1 = C2.5 v, measure v w1 with v w2 = 5 v p-p @ f = 10 khz, code1 = 20 h , code 2 = 3f h , r ab = 10 k ? /50 k ? /100 k ? C86/C73/C68 db interface timing characteristics (applies to all parts) 5, 10 clock cycle time (t cyc )t 1 20 ns cs setup time t 2 10 ns clk shutdown time to cs rise t 3 1t cyc input clock pulsewidth t 4 , t 5 clock level high or low 10 ns data setup time t 6 from positive clk transition 5 ns data hold time t 7 from positive clk transition 5 ns cs to sdo-spi line acquire t 8 40 ns cs to sdo-spi line release t 9 50 ns clk to sdo propagation delay 11 t 10 r p = 2.2 k ? , c l < 20 pf 50 ns clk to sdo data hold time t 11 r p = 2.2 k ? , c l < 20 pf 0 ns cs high pulsewidth 12 t 12 10 ns cs high to cs high 12 t 13 4t cyc rdy rise to cs fall t 14 0ns cs rise to rdy fall time t 15 0.1 0.15 ms read/store to nonvolatile eemem 13 t 16 applies to command 2 h , 3 h , 9 h 25 ms cs rise to clock rise/fall setup t 17 10 ns preset pulsewidth (asynchronous) t prw not shown in timing diagram 50 ns preset response time to rdy high t presp pr pulsed low to refreshed wiper positions 70 s flash/ee memory reliability endurance 14 100 k cycles data retention 15 100 years notes 1 typicals represent average readings at 25 c and v dd = 5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. i w 50 a @ v dd = 2.7 v for the r ab = 10 k ? version, i w 50 a for the r ab = 50 k ? and i w 25 a for the r ab = 100 k ? version. see test circuit 1. 3 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = v ss . dnl specification limits of C1 lsb minimum are guaranteed monotonic operating conditions. see test circuit 2. 4 resistor terminals a, b, and w have no limitations on polarity with respect to each other. dual supply operation enables ground referenced bipolar signal adjustment. 5 guaranteed by design and not subject to production test. 6 common mode leakage current is a measure of the dc leakage from any terminal b and w to a common mode bias level of v dd /2. 7 transfer (xfr) mode current is not continuous. current consumed while eemem locations are read and transferred to the rdac regi ster. see tpc 19. 8 p diss is calculated from (i dd v dd ) + (i ss v ss ) 9 all dynamic characteristics use v dd = +2.5 v and v ss = C2.5 v 10 see timing diagram for location of measured values. all input control voltages are specified with t r = t f = 2.5 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. switching characteristics are measured using both v dd = 3 v and 5 v. 11 propagation delay depends on value of v dd , r pull_up , and c l see applications text. 12 valid for commands that do not activate the rdy pin. 13 rdy pin low only for commands 2, 3, 8, 9, 10, and the pr hardware pulse: cmd_8 1 ms; cmd_9, 10 0.12 ms; cmd_2, 3 20 ms. device operation at t a = C40 o c and v dd < 3 v extends the save time to 35 ms. 14 endurance is qualified to 100,000 cycles as per jedec std. 22, method a117 and measured at C40 c, +25 c, and +85 c, typical endurance at 25 c is 700,000 cycles. 15 retention lifetime equivalent at junction temperature (t j ) = 55 c as per jedec std. 22, method a117. retention lifetime based on an activation energy of 0.6 v will derate with junction temperature as shown in figure 11 in the flash/ee memory description section of this data sheet. the AD5233 contains 9,646 transistors. die size: 69 mil 115 mil, 7,993 sq. mil. specifications subject to change without notice.
rev. 0 AD5233 C4C cpol = 1 t 12 t 13 t 3 t 17 t 9 t 11 t 5 t 4 t 2 t 1 clk t 8 * msb lsb out msb lsb rdy t 10 t 7 t 6 t 14 t 15 t 16 *n ot defined, but normally lsb of character previously transmitted. the cpol = 1 microcontroller command aligns the incoming data to the positive edge of the clock. cs sdo sdi t 10 figure 2a. cpha = 1 timing diagram t 12 t 13 t 3 t 17 t 9 t 5 t 4 t 2 t 1 clk cpol = 0 t 8 msb out lsb sdo msb in lsb sdi rdy t 10 t 7 t 6 t 14 t 15 t 16 * not defined, but normally msb of character just received. the cpol = 0 microcontroller command aligns the incoming data to the positive edge of the clock. * cs t 11 figure 2b. cpha = 0 timing diagram
rev. 0 AD5233 C5C absolute maximum ratings 1 (t a = 25 c, unless otherwise noted.) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +7 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v, C7 v v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v a , v b , v w to gnd . . . . . . . . . . . . . v ss C 0.3 v, v dd + 0.3 v aCb, aCw, bCw, intermittent 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ma digital inputs and output voltage to gnd . . C0.3 v, v dd + 0.3 v operating temperature range 3 . . . . . . . . . . . C40 c to +85 c maximum junction temperature (t j max) . . . . . . . . . 150 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c thermal resistance junction-to-ambient ja , tssop-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 c/w thermal resistance junction-to-case jc , tssop-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 c/w package power dissipation = (t j max C t a )/ ja notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 3 includes programming of nonvolatile memory. ordering guide number of r ab temperature package package ordering model channels (k ) range description option quantity top mark * AD5233bru10 4 10 C40 c to +85 c tssop-24 ru-24 96 5233b10 AD5233bru10-reel7 4 10 C40 c to +85 c tssop-24 ru-24 1,000 5233b10 AD5233bru50 4 50 C40 c to +85 c tssop-24 ru-24 96 5233b50 AD5233bru50-reel7 4 50 C40 c to +85 c tssop-24 ru-24 1,000 5233b50 AD5233bru100 4 100 C40 c to +85 c tssop-24 ru-24 96 5233bc AD5233bru100-reel7 4 100 C40 c to +85 c tssop-24 ru-24 1,000 5233bc * line 1 contains adi logo symbol and the date code yyww, line 2 contains detail model number listed in this column. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD5233 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. 0 AD5233 C6C pin configuration 1 clk sdi sdo v ss gnd a1 rdy cs pr wp v dd a4 w4 ad5231 o1 w1 o2 b4 b1 a3 a2 w3 w2 b3 b2 top view (not to scale) 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 AD5233 pin function descriptions pin no. mnemonic description 1 o1 nonvolatile digital output #1. address(o1) = 4 h , data bit position d0, defaults to logic 1 initially. 2 clk serial input register clock pin. shifts in one bit at a time on positive clock edges. 3 sdi serial data input pin. shifts in one bit at a time on positive clock clk edges. msb loaded first. 4 sdo serial data output pin. open drain output requires external pull-up resistor. commands 9 and 10 activate the sdo output. see table iii, instruction operation truth table. other commands shift out the previously loaded sdi bit pattern delayed by 16 clock pulses. this allows daisy-chain operation of multiple packages. 5 gnd ground pin, logic ground reference 6v ss negative supply. connect to 0 v for single supply applications. 7 a1 a terminal of rdac1 8 w1 wiper terminal of rdac1, address(rdac1) = 0 h 9 b1 b terminal of rdac1 10 a2 a terminal of rdac2 11 w2 wiper terminal of rdac2, address(rdac2) = 1 h 12 b2 b terminal of rdac2 13 b3 b terminal of rdac3 14 w3 wiper terminal of rdac3, address(rdac3) = 2 h 15 a3 a terminal of rdac3 16 b4 b terminal of rdac4 17 w4 wiper terminal of rdac4, address(rdac4) = 3 h 18 a4 a terminal of rdac4 19 v dd positive power supply pin 20 wp write protect pin. when active low, wp prevents any changes to the present contents except pr strobe, cmd_1, and cmd_8 will refresh the rdac register from eemem. execute a nop instruction before returning to wp high. 21 pr hardware override preset pin. refreshes the scratch pad register with current contents of the eemem register. factory default loads midscale 32 10 until eemem loaded with a new value by the user ( pr is activated at the logic high transition). 22 cs serial register chip select active low. serial register operation takes place when cs returns to logic high. 23 rdy ready. active high open drain output. identifies completion of commands 2, 3, 8, 9, 10, and pr . 24 o2 nonvolatile digital output #2. address(o2) = 4 h , data bit position d1, defaults to logic 1 initially.
rev. 0 C7C typical performance characteristics AD5233 code decimal inl error lsb 0.20 0 16 32 64 0.10 0 0.10 0.20 48 0.15 0.05 0.05 0.15 t a = 40 c t a = +25 c t a = +85 c tpc 1. inl vs. code, t a = C40 c, +25 c, +85 c overlay, r ab = 10 k ? code decimal r-dnl lsb 0.20 0 16 32 64 0.10 0 0.10 0.20 48 0.15 0.05 0.05 0.15 t a = 40 c t a = +85 c t a = +25 c v dd = 5v, v ss = 0v tpc 4. r-dnl vs. code, t a = C40 c, +25 c, +85 c overlay, r ab = 10 k ? code decimal r w 80 0 16 32 64 40 0 48 60 20 v dd = 2.7v, v ss = 0v t a = 25 c tpc 7. wiper on-resistance vs. code code decimal dnl error lsb 0.20 0 16 32 64 0.10 0 0.10 0.20 48 0.15 0.05 0.05 0.15 t a = 40 c t a = +25 c t a = +85 c tpc 2. dnl vs. code, t a = C40 c, +25 c, +85 c overlay, r ab = 10 k ? code decimal rheostat mode tempco ppm/ c 3000 0 16 32 64 2000 1000 0 48 2500 1500 500 v dd = 5v, v ss = 0v t a = 40 c to +85 c tpc 5. ? r wb / ? t vs. code, r ab = 10 k ? temperature c current a 4 40 100 1 1 2 0 3 20 0 20406080 i dd @ v dd /v ss = 5v/0v i dd @ v dd /v ss = 2.7v/0v i ss @ v dd /v ss = 2.7v/0v i ss @ v dd /v ss = 5v/0v tpc 8. i dd vs. temperature, r ab = 10 k ? code decimal r-inl lsb 0.20 0 16 32 64 0.10 0 0.10 0.20 48 0.15 0.05 0.05 0.15 t a = 40 c t a = +25 c t a = +85 c v dd = 5v, v ss = 0v tpc 3. r-inl vs. code, t a = C40 c, +25 c, +85 c overlay, r ab = 10 k ? code decimal potentiometer mode tempco ppm/ c 1600 0 16 32 64 800 0 48 1200 400 v dd = 5v, v ss = 0v t a = 40 c to +85 c v a = 2v v b = 0v tpc 6. ? v wb / ? t vs. code, r ab = 10 k ? clock frequency mhz i dd ma 0.25 0 12 0.10 0 0.15 0.05 0.20 246810 v dd = 5v v ss = 0v zero-scale full-scale midscale 0.30 tpc 9. i dd vs. clock frequency, r ab = 10 k ?
rev. 0 AD5233 C8C frequency hz gain db 3.0 1k 1m 6.0 12.0 3.0 9.0 0 10k 100k f 3db = 600khz, r ab = 10k v dd /v ss = 2.5v v a /1vms d = midscale f 3db = 66khz f 3db = 132khz, r ab = 50k tpc 10. C3 db bandwidth vs. resis- tance. test circuit 7. frequency hz amplitude db 0 100 1m 30 42 24 36 12 1k 10k 100k code 20 h 6 18 01 h 02 h 04 h 08 h 10 h tpc 13. gain vs. frequency vs. code, r ab = 50 k ? . test circuit 7. v a v w 0.5v/div midscale 100 s/div expected va l u e v dd = 5v v a = 2.25v v b = 0v tpc 16. power-on reset, v a = 2.25 v, code = 101010 b frequency hz thd + noise % 0.05 10 100k 0.02 0 0.03 0.01 0.04 100 1k 10k r ab = 10k 100k 50k v dd /v ss = 2.5v v a = 1v ms tpc 11. total harmonic distortion vs. frequency frequency hz amplitude db 0 100 1m 30 42 24 36 12 1k 10k 100k code 20 h 6 18 01 h 02 h 04 h 08 h 10 h tpc 14. gain vs. frequency vs. code, r ab = 100 k ? . test circuit 7. 2.60 2.56 2.52 2.48 2.44 2.40 0 5 150 511 100 200 2.58 2.54 2.50 2.46 2.42 250 300 350 400 450 time s v out v v dd = v a = 5v v ss = v b = 0v code = 20 h to 1f h tpc 17. midscale glitch energy, code 20 h to 1f h frequency hz amplitude db 0 100 10m 30 42 24 36 12 1k 10k 100k 6 18 1m 01 h 02 h 04 h 08 h 10 h code 20 h tpc 12. gain vs. frequency vs. code, r ab = 10 ? . test circuit 7. frequency hz psrr db 80 0.1k 10m 20 0 30 10 50 1k 10k 100k 60 40 70 1m v dd = 5v 100mv ac v ss = 0v, v a = 5v, v b = 0v measured at v w with code = 200 h r ab = 10k r ab = 50k r ab = 100k tpc 15. psrr vs. frequency cs clk sdi i dd 20ma/div 4ms/div 5v/div 5v/div 5v/div 0.(#6 0%?& .

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rev. 0 AD5233 C9C cs clk sdi i dd * 2ma/div *supp ly current returns to minimum power consumption if instruction #0 (nop) is executed immediately after instruction #1 (read eemem) 4ms/div 5v/div 5v/div 5v/div tpc 19. i dd vs. time (read) program mode 1 0.01 0.1 code decimal theoretical i wb_max ma 0 8 24 64 16 32 40 48 56 10 100 r ab = 10k r ab = 50k r ab = 100k v a = v b = open t a = 25 c 0.(+ >@ ( offset bias offset gnd ab dut w 5v v in v out op279 test circuit 5. inverting gain offset bias offset gnd ab dut w 5v v in v out op279 test circuit 6. noninverting gain offset gnd a b dut w +15v v in v out op42 15v 2.5v test circuit 7. gain vs. frequency + _ dut code = h 0.1v v bias r sw = 0.1v i sw i sw w b a = nc 0 (
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7! test circuits test circuits 1 to 10 define the test conditions used in the product specifications table. a w b nc i w dut v ms nc = no connect test circuit 1. resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) a w b dut v ms v+ v+ = v dd 1lsb = v+/2 n test circuit 2. potentiometer divider nonlinearity error (inl, dnl) a w b dut i w v ms1 v ms2 v w r w = [ v ms1 v ms2 ] /i w test circuit 3. wiper resistance a w b v ms v+ = v dd 10% psrr (db) = 20 log v ms v dd ( ) ~ v a v dd v ms % v dd % pss (%/%) = v+ test circuit 4. power supply sensitivity (pss, psrr)
rev. 0 AD5233 C10C scratch pad and eemem programming the scratch pad register (rdac register) directly controls the position of the digital potentiometer wiper. when the scratch pad register is loaded with all zeros the wiper will be connected to the b-terminal of the variable resistor. when the scratch pad regis- ter is loaded with midscale code (one-half of full-scale position) the wiper will be connected to the middle of the variable resistor. and when the scratch pad is loaded with full-scale code, all ones, the wiper will connect to the a-terminal. since the scratch pad register is a standard logic register, there is no restriction on the number of changes allowed. the eemem registers have a program erase/write cycle limitation described in the flash/eemem reliability section. basic operation the basic mode of setting the variable resistor wiper position (programming the scratch pad register) is accomplished by loading the serial data input register with the command instruction #11, which includes the desired wiper position data. when the desired wiper position is determined, the user may load the serial data input register with the command instruction #2, which makes a copy of the desired wiper position data into the nonvolatile eemem register. after 25 ms the wiper posi tion will be permanently stored in the nonvolatile eemem location. table i provides an application-programming exam ple listing the sequence of serial data input (sdi) words and the serial data output appearing at the sdo pin in hexadecimal format. table i. set and save rdac data to eemem register sdi sdo action b010 h xxxx h loads data 10 h into rdac1 register, wiper w1 moves to 1/4 full-scale position. 20xx h b010 h saves copy of rdac1 register contents into eemem1 register. at system power on, the scratch pad register is automatically refreshed with the value last saved in the eemem register. the factory preset eemem value is midscale but thereafter, the eemem value can be changed by user. during operation, the scratch pad (wiper) register can also be refreshed with the current contents of the nonvolatile eemem register under hardware control by pulsing the pr pin without activating instruction 1 or 8. beware that the pr pulse first sets the wiper at midscale when brought to logic zero, and then on the positive transition to logic high, it reloads the rdac wiper register with the contents of eemem. many additional advanced pro- gramming commands are available to simplify the variable resistor adjustment process (see table iii). for example, the wiper position can be changed one step at a time by using the increment/dec- rement instruction or by 6 db at a time with the shift left/right instruction command. once an increment, decrement or shift command has been loaded into the shift register, subsequent cs strobes will repeat this command. this is useful for push button control applications. see the advanced control modes section following the instruction operation truth table. a serial data output sdo pin is available for daisy chaining and for readout of the internal register contents. the serial input data register uses a 24-bit [instruction/address/data] word format. operational overview the AD5233 digital potentiometer is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of v ss < v term < v dd . the basic voltage range is limited to a |v dd C v ss | < 5.5 v. the digital potentiometer wiper position is determined by the rdac register contents. the rdac register acts as a scratch pad register allowing as many value changes as necessary to place the potentiometer wiper in the correct position. the scratch pad register can be programmed with any position value using the standard spi serial interface mode by loading the complete representative data word. once a desirable position is determined this value can be saved into a eemem register. thereafter the wiper position will always be set at that position for any future on-off-on power supply sequence. the eemem save process takes approximately 25 ms, during this time the shift register is locked preventing any changes from taking place. the rdy pin indicates the completion of this eemem save. there are 16 instructions which facilitates users programming needs, (refer to table iii). the instructions are: 0. do nothing 1. restore eemem setting to rdac 2. save rdac setting to eemem 3. save user data or rdac setting to eemem 4. decrement 6 db 5. decrement all 6 db 6. decrement one step 7. decrement all one step 8. reset eemem setting to rdac 9. read eemem to sdo 10. read wiper setting to sdo 11. write data to rdac 12. increment 6 db 13. increment all 6 db 14. increment one step 15. increment all one step test circuits (continued) dut v ss i cm w b v dd nc nc v cm gnd a nc = no connect test circuit 9. common-mode leakage current ~ v in a1 rdac1 w1 b1 nc nc = no connect v ss v dd a2 rdac2 w2 b2 v out c ta = 20 log v out v in () test circuit 10. analog crosstalk
rev. 0 AD5233 C11C eemem protection write protect ( wp ) disables any changes of the scratch pad register contents regardless of the software commands, except that the eemem setting can be refreshed and overwrite wp by using commands 8 and pr . pulse. therefore, the write-protect ( wp ) pin provides a hardware eemem protection feature. to disable wp , it is recommended to execute a nop command before returning wp to logic high. digital input/output configuration all digital inputs are esd protected high input impedance that can be driven directly from most digital sources. active at logic low, pr and wp must be biased to v dd if they are not used. there are no internal pull-up resistors present on any digital input pins. since the device may be detached from the driving source once it is programmed, adding pull-up resistance in the digital input pins is a good way to avoid falsely triggering the floating pins in a noisy environment. the sdo and rdy pins are open drain digital outputs where pull- up resistors are needed only if using these functions. a resistor value in the range of 1 k ? to 10 k ? is a proper choice which bal- ances the power and switching speed trade off. serial data interface the AD5233 contains a four-wire spi-compatible digital interface (sdi, sdo, cs , and clk). the AD5233 uses a 16-bit serial data word loaded msb first. the format of the spi-compatible word is shown in table ii. the chip select cs pin needs to be held low until the complete data word is loaded into the sdi pin. when cs returns high, the serial data word is decoded according to the instructions in table iii. the command bits (cx) control the operation of the digital potentiometer. the address bits (ax) determine which register is activated. the data bits (dx) are the values that are loaded into the decoded register. to program rdac 1C4, only the 6 lsb databits are used. table v provides an address map of the eemem locations. the last instruction executed prior to a period of no programming activity should be the no operation (nop) instruction 0. this will place the internal logic circuitry in a minimum power dissipation state. va l i d command counter command processor and address decode serial register clk sdi 5v r pullup sdo gnd pr wp cs AD5233 (for daisy chain only) figure 3. equivalent digital input-output logic the equivalent serial data input and output logic is shown in figure 3. the open drain output sdo is disabled whenever chip select cs is logic high. the spi interface can be used in two slave modes cpha = 1, cpol = 1, and cpha = 0, cpol = 0. cpha, and cpol refer to the control bits, which dictate spi timing in these microconverter ? s and microprocessors: aduc812/824, m68hc11, and mc68hc16r1/916r1. esd protection of the digital inputs is shown in figures 4a and 4b. logic pins v dd gnd input 300 figure 4a. equivalent esd digital input protection v dd gnd input 300 wp u figure 4b. equivalent wp input protection daisy-chain operation the serial data output pin (sdo) serves two purposes. it can be used to read out the contents of the wiper setting and eemem values using instructions 10 and 9 respectively. the remaining 14 instructions (#0C#8, #11C#15) are valid for daisy chaining multiple devices in simultaneous operations. daisy chaining minimizes the number of port pins required from the controlling ic (see figure 5). the sdo pin contains an open drain n-ch fet that requires a pull-up resistor, if this function is used. as shown in figure 5, users need to tie the sdo pin of one package to the sdi pin of the next package. users may need to increase the clock period because the pull-up resistor and the capacitive loading at the sdo-sdi interface may require an additional time delay between subsequent packages. when two AD5233s are daisy chained 32 bits of data are required. the first 16 bits go to u2 and the second 16 bits go to u1. the 16 bits are formatted to contain the 4-bit instruction, followed by the 4-bit address, then 8-bits of data. the cs should be kept low until all 32 bits are clocked into their respective serial registers. the cs is then pulled high to complete the operation. sdi sdo clk +v r p 2k c sdi sdo clk cs cs u1 u2 AD5233 AD5233 figure 5. daisy chain configuration using sdo microconverter is a registered trademark of analog devices, inc.
rev. 0 AD5233 C12C table ii. 16-bit serial data word msb instruction byte lsb data byte rdac c3 c2 c1 c0 * 0 0 a1 a0 x x d5d4d3d2d1d0 eemem c3c2c1c0a3 a2 a1 a0 d7d6d5d4d3d2d1d0 * command bits are c0 to c3. address bits are a3-a0. data bits d0 to d5 are applicable to rdac wiper register whereas d0 to d7 ar e applicable to eemem register. command instruction codes are defined in table iii. table iii. instruction operation truth table 1, 2, 3 instruction byte 0 data byte 0 inst. b16 ? ? ? ? ???? ? ? ? ? ? ? ? ? ? ? ? b8 b7 b6 b5 b4 b3 b2 b1 b0 no. c3 c2 c1 c0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0000 xxxx x xxxxxxx nop: do nothing. see table x for programming example. 1 000100a1a0x xxxxxxx write content of eemem to rdac register. this command leaves device in the read program power state. to return part to the idle state, perform nop instruction #0. see table x. 2 001000a1a0x xxxxxxx save wiper setting: write contents of rdac at address a1 a0 to eemem. see table ix. 3 4 0011a3a2a1a0d7d6d5d4d3d2d1d0write contents of serial register data byte 0 (total 8-bit) to eemem(addr). see table xii. 4 5 010000a1aox xxxxxxx decrement 6 db: right shift contents of rdac register, stops at all zeros. 5 5 0101 xxxx x xxxxxxx decrement all 6 db: right shift contents of all rdac registers, stops at all zeros. 6 5 011000a1a0x xxxxxxx decrement content of rdac register by one, stops at all zero. 7 5 0111 xxxx x xxxxxxx decrement contents of all rdac registers by one, stops at all zero. 8 1000 xxxx x xxxxxxx reset: load all rdacs with their corresponding eemem previously-saved values 9 1001a3a2a1a0x xxxxxxx tr ansfer content of eemem(addr) to serial register data byte 0 and previously stored data can be ` read out from sdo pin. see table xiii. 10 101000a1a0x xxxxxxx tr ansfer content of rdac (addr) to serial register data byte 0 and wiper setting can be read out from sdo pin. see table xiv. 11 101100a1a0x xd5d4d3d2d1d0 write content of serial register data byte 0 (total 6-bit) to rdac. see table viii. 12 5 110000a1a0x xxxxxxx increment 6 db: left shift content of rdac register, stops at all ones. see table xi. 13 5 1101 xxxx x xxxxxxx increment all 6 db: left shift contents of rdac registers, stops at all ones. 14 5 111000a1a0x xxxxxxx increment content of rdac register by one, stops at all ones. see table ix. 15 5 1111 xxxx x xxxxxxx increment contents of all rdac registers by one, stops at all ones. notes 1 the sdo output shifts out the last 16-bits of data clocked into the serial register for daisy-chain operation. exception, any i nstruction that follows instruction #9 or #10, see details of these instruction for proper usage. 2 the rdac register is a volatile scratch pad register that is automatically refreshed at power on from the corresponding non-vol atile eemem register. 3 execution of the above operations takes place when the cs strobe returns to logic high. 4 instruction #3 write one data byte (8-bit data) to eemem. but in the cases of addresses 0, 1, 2, 3 only the last 6 bits are val id for wiper position setting. 5 the increment, decrement and shift commands ignore the contents of the shift register data byte 0.
rev. 0 AD5233 C13C v dd gnd outputs o1 and o2 pins figure 7. logic outputs o1 and o2. advanced control modes the AD5233 digital potentiometer contains a set of user programming features to address the wide applications avail able to these universal adjustment devices. key programming features include: ? scratch pad programming to any desirable values ? nonvolatile memory storage of the present scratch pad rdac register value into the eemem register ? i ncrement and decrement instructions for rdac wiper register ? left and right bit shift of rdac wiper register to achieve 6 db level changes ? eleven extra bytes of user addressable nonvolatile memory linear increment and decrement commands the increment and decrement commands (#14, #15, #6, #7) are useful for linear step adjustment applications. these com- mands simplify microcontroller software coding by allowing the controller to just send an increment or decrement command to the device. for the increment command, executing instruction #14 with proper address will automatically move the wiper to the next resistance segment position. instruction #15 performs the same function except that address does not need to be speci- fied. all rdacs are changed at the same time. logarithmic taper mode adjustment ( 6 db/step) four programming instructions produce logarithmic taper incre- ment and decrement wiper. these settings are activated by the 6 db increment and 6 db decrement instructions #12, #13, #4, and #5 respectively. for example, starting at zero scale, executing eight increment instructions #12 will move the wiper in 6 db per step from the 0% to full scale r ab . the 6 db increment instruc- tion doubles the value of the rdac register content each time the command is executed. when the wiper position is near the maximum setting, the last 6 db increment instruction causes the wiper to go to the full-scale 63 10 code position. further 6 db per increment instruction will no longer change the wiper position beyond its full scale. 6 db step increment and decrement are achieved by shifting the bit internally to the left and right respec- tively. the following information explains the nonideal 6 db step adjustment at certain conditions. table iv illustrates the operation of the shifting function on the rdac register data bits. each line going down the table represents a successive shift operation. note that the left shift #12 and #13 commands were modified such that if the data in the rdac register is equal to zero, and the data is left shifted, the rdac register is then set terminal voltage operation range the AD5233 positive v dd and negative v ss power supply defines the boundary conditions for proper 3-terminal digital potentiom- eter operation. supply signals present on terminals a, b, and w that exceed v dd or v ss will be clamped by the internal forward biased diodes (see figure 6). v ss v dd a w b figure 6. maximum terminal voltages set by v dd and v ss the ground pin of the AD5233 device is primarily used as a digital ground reference that needs to be tied to the pcbs common ground. the digital input control signals to the AD5233 must be referenced to the device ground pin (gnd), and satisfy the logic level defined in the specification table of this data sheet. an internal level shift circuit ensures that the common-mode voltage range of the three-terminals extends from v ss to v dd regardless of the digital input level. power up sequence since there are diodes to limit the voltage compliance at termi nals a, b, and w (see figure 6) it is important to power v dd /v ss first before applying any voltages to terminals a, b, and w. otherw ise, the diode will be forward biased such that v dd /v ss will be pow ered unintentionally. for example, applying 5 v across terminals a and b prior to v dd will cause the v dd terminal to exhibit 4.3 v. it is not destructive to the device, but it may affect the rest of the users system. as a result, the ideal power up sequence is in the following order: gnd, v dd , v ss , digital inputs, and v a/b/w . the order of powering v a , v b , v w , and digital inputs is not important as long as they are powered after v dd /v ss . regardless of the power up sequence and the ramp rates of the power supplies, once v dd /v ss are powered, the power-on reset remains effective, which retrieves eemem saved values to the rdac registers. latched digital outputs a pair of digital outputs, o1 and o2, are available on the AD5233 that provide a nonvolatile logic 0 or logic 1 setting. o1 and o2 are standard cmos logic outputs shown in figure 7. these outputs are ideal to replace functions often provided by dip switches. in addition, they can be used to drive other standard cmos logic controlled parts that need an occasional setting change. o1 and o2, are defaulted to logic 1 initially.
rev. 0 AD5233 C14C to code 1. similarly, if the data in the rdac register is greater than or equal to mid-scale, and the data is left shifted, then the data in the rdac register is automatically set to full-scale. this makes the left shift function as ideal logarithmic adjustment as is possible. the right shift #4 and #5 commands will be ideal only if the lsb is zero (i.e. ideal logarithmicno error). if the lsb is a one then the right shift function generates a linear half lsb error, which translates to a numbers of bits dependent logarithmic error as shown in figure 8. the plot shows the error of the odd numbers of bits for AD5233. table iv. detail left and right shift functions for 6 db step increment and decrement left shift right shift 00 0000 11 1111 00 0001 01 1111 00 0010 00 1111 00 0100 00 0111 00 1000 00 0011 01 0000 00 0001 10 0000 00 0000 11 1111 00 0000 11 1111 00 0000 actual conformance to a logarithmic curve between the data contents in the rdac register and the wiper position for each right shift #4 and #5 command execution contains an error only for odd numbers of bits. even numbers of bits are ideal. the graph in figure 8 shows plots of log_error [i.e. 20 log 10 (error/code)] AD5233. for example, code 3 log_error = 20 log 10 (0.5/3) = C15.56 db, which is the worst case. the plot of log_error is more significant at the lower codes. code 0 0 db 20 30 50 10 5 101520253035404550556065 40 15.56db @ code 3 figure 8. plot of log_error conformance for odd numbers of bits only (even numbers of bits is ideal) the AD5233 contains additional internal user storage registers (eemem) for saving constants and other 8-bit data. table v provides an address map of the internal storage registers shown in the functional block diagram as eemem1, eemem2, and 11 bytes of user eemem. table v. eemem address map eemem number address eemem content for 1 0000 rdac1 1, 2 2 0001 rdac2 1, 2 3 0010 rdac3 1, 2 4 0011 rdac4 1, 2 5 0100 o1 and o2 3 6 0101 user1 4 7 0110 user2 ::: 15 1110 user10 16 1111 user11 notes 1 rdac data stored in the eemem location is transferred to the rdac register at power on, or when instructions inst#1, #8, and pr are executed. 2 execution of instruction #1 leaves the device in the read mode power con- sumption state. after the last instruction #1 is executed, the user should perform a nop, instruction #0 to return the device to the low power idling state. 3 o1 and o2 data stored in eemem locations are transferred to their corresponding digital register at power on, or when instructions #1 and #8 are executed. 4 user <#> are internal nonvolatile eemem registers available to store and retrieve constants and other 8-bit information using inst#3 and inst#9 respectively. rdac structure the patent pending rdac contains multiple strings of equal resistor segments, with an array of analog switches, that act as the wiper connection. the number of positions is the resolution of the device. the AD5233 has 64 connection points allowing it to provide better than 1.5% set ability resolution. figure 9 shows an equivalent structure of the connections between the three termi nals of the rdac. the sw a and sw b will always be on, while one of the switches sw(0) to sw(2 n C 1) will be on one at a time depending on the resistance position decoded from the data b its. since the switch is not ideal, there is a 15 ? wiper resistance, r w . wiper resistance is a function of supply voltage and temperature. the lower the supply voltage or the higher the temperature, the higher the resulting wiper resistance. users should be aware of the wiper resistance dynamics if accurate prediction of the output resistance is needed. sw (1) sw (0) sw b b sw a sw(2 n 1) a w sw(2 n 2) rdac wiper register and decoder r s = r ab /2 n r s digital circuitry omitted for clarity r s r s figure 9. equivalent rdac structure (patent pending) right shift (C6 db/step) left shift (+6 db/step)
rev. 0 AD5233 C15C programming the variable resistor rheostat operation the nominal resistance of the rdac between terminals a-and-b, r ab , are available with 10 k ? , 50 k ? and 100 k ? with 64 posi- tions (6-bit resolution). the final digit(s) of the part number determine the nominal resistance value, e.g., 10 k ? = 10; 50 k ? = 50, 100 k ? = 100. the 6-bit data word in the rdac latch is decoded to select one of the 64 possible settings. the following discussion describes the calculation of resistance r wb at different codes of a 10 k ? part. for v dd = 5 v, the wipers first connection starts at the b terminal for data 00 h . r wb (0) is 15 ? because of the wiper resistance and it is independent to the nominal resistance. the second connection is the first tap point where r wb (1) becomes 156 ? + 15 ? = 171 ? for data 01 h . the third connection is the next tap point representing r wb (2) = 312 + 15 = 327 ? for data 02 h and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at r wb (63) = 9858 ? . see f igure 9 for a simplified diagram of the equivalent rdac circuit. when r wb is used, the a-terminal can be let floating or tied to the wiper. code decimal 100 75 0 063 16 32 48 50 25 r wb r wa r wa (d), r wb (d), % of full-scale r ab figure 10. r wa (d) and r wb (d) vs. decimal code the general equation, which determines the programmed output resistance between w and b, is: rd d rr wb ab w () = + 64 (1) where d is the decimal equivalent of the data contained in the rdac register, r ab is the nominal resistance between terminals a-and-b, and r w is the wiper resistance. for example, the following output resistance values will be set for the following rdac latch codes with v dd = 5 v (applies to r ab = 10 k ? digital potentiometers): table vi. r wb (d) at selected codes for r ab = 10 k d (dec) r wb (d) ( ) output state 63 9858 full-scale 32 5015 mid-scale 1 171 1 lsb 0 15 zero-scale (wiper contact resistance) note that in the zero-scale condition a finite wiper resistance of 15 ? is present. care should be taken to limit the current flow between w and b in this state to no more than 20 ma to avoid degradation or possible destruction of the internal switches. like the mechanical potentiometer the rdac replaces, the AD5233 parts are totally symmetrical. the resistance between the wiper w and terminal a also produces a digitally controlled complementary resistance r wa . figure 10 shows the symmetrical programmability of the various terminal connections. when r wa is used, the bCterminal can be let floating or tied to the wiper. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. the general transfer equation for this operation is: rd d rr wa ab w () = ? + 64 64 (2) for example, the following output resistance values will be set for the following rdac latch codes with v dd = 5 v (applies to r ab = 10 k ? digital potentiometers): table vii. r wa (d) at selected codes for r ab = 10 k d (dec) r wa (d) ( ) output state 63 171 full-scale 32 5015 mid-scale 1 9858 1 lsb 0 10015 zero-scale channel-to-channel r ab matching is better than 1%. the change in r ab with temperature has a 600 ppm/ c temperature coefficient. programming the potentiometer divider voltage output operation the digital potentiometer can be configured to generate an output voltage at the wiper terminal which is proportional to the input voltages applied to terminals a and b. for example connecting aCterminal to 5 v and bCterminal to ground pro duces an output voltage at the wiper which can be any value starting at 0 v up to 5 v. each lsb of voltage is equal to the volt age applied across terminal ab divided by the 2 n position resolution of the potentiometer divider. since AD5233 can also be supplied by dual supplies, the general equation defining the output voltage at v w with respect to ground for any given input voltages applied to terminals a and b is: vd d vv wabb () = + 64 (3) equation 3 assumes v w is buffered so that the effect of wiper resistance is nulled. operation of the digital potentiometer in the divider mode results in more accurate operation over tempera- ture. here the output voltage is dependent on the ratio of the internal resistors and not the absolute value, therefore, the drift improves to 15 ppm/ c. there is no voltage polarity restriction between terminals a, b, and w as long as the terminal voltage (v term ) stays within v ss < v term < v dd . programming examples the following programming examples illustrate the typical sequence of events for various features of the AD5233. users should refer to table iii for the instructions and data word format. the instruc- tion numbers, addresses, and data appearing at sdi and sdo pins are displayed in hexadecimal format in the following examples.
rev. 0 AD5233 C16C table viii. scratch pad programming sdi sdo action b010 h xxxx h loads data 10 h into rdac1 register, wiper w1 moves to 1/4 full-scale position table ix. incrementing rdac1 followed by storing the wiper setting to eemem1 sdi sdo action b010 h xxxx h loads data 10 h into rdac1 register, wiper w1 moves to 1/4 full-scale position e0xx h b010 h increments rdac1 register by one to 11 h e0xx h e0xx h increments rdac1 register by one to 12 h continue until desired wiper position reached 20xx h xxxx h saves rdac1 register data into eemem1 optionally tie w p to gnd to protect eemem values table x. restoring eemem1 value to rdac1 register eemem value for rdac can be restored by power on, strobing pr pin, or two different commands as shown below sdi sdo action 10xx h xxxx h restores eemem1 value to rdac1 register 00xx h 10xx h nop. recommended command to minimize power consumption 8xxx h 00xx h reset eemem1 value to rdac1 register table xi using left shift by one to increment 6 db step sdi sdo action c0xx h xxxx h moves wiper to double the present data contained in rdac1 register table xii. storing additional user data in eemem sdi sdo action 35aa h xxxx h stores data aa h into spare eemem6 location user1 (allowable to address in 11 locations with maximum 8 bits of data) 3655 h 35aa h stores data 55 h into spare eemem7 location user2. (allowable to address 11 locations with maximum 8 bits of data) table xiii. reading back data from various memory locations sdi sdo action 95xx h xxxx h prepares data read from user1 location 00xx h 95aa h nop instruction #0 sends 16-bit word out of sdo where the last 8 bits contain the contents of user1 location. nop command ensures device returns to idle power dissipation state table xiv. reading back wiper settings sdi sdo action b020 h xxxx h sets rdac1 to mid-scale c0xx h b020 h doubles rdac1 from mid-scale to full-scale (left shift instruction) a0xx h c0xx h prepares reading wiper setting from rdac1 register xxxx h a03f h readback full-scale value from rdac1 register flash/eemem reliability the flash/ee memory array on the AD5233 is fully qualified for two key flash/ee memory characteristics, namely flash/ee memory cycling endurance and flash/ee memory data retention. endurance quantifies the ability of the flash/ee memory to be cycled through many program, read, and erase cycles. in real terms, a single endurance cycle is composed of four independent, sequential events. these events are defined as: 1. initial page erase sequence 2. read/verify sequence 3. byte program sequence 4. second read/verify sequence during reliability qualification flash/ee memory is cycled from 00 h to 3f h until a first fail is recorded signifying the endurance limit of the on-chip flash/ee memory. as indicated in the specification pages of this data sheet, the AD5233 flash/ee memory endurance qualification has been carried out in accordance with jedec specification a117 over the industrial temperature range of C40 c to +85 c. the results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with an endurance figure of 700,000 cycles being typical of operation at 25 c. retention quantifies the ability of the flash/ee memory to retain its programmed data over time. again, the AD5233 has been qualified in accordance with the formal jedec retention lifetime specification (a117) at a specific junction temperature (t j = 55 c). as part of this qualification procedure, the flash/ee memory is cycled to its specified endurance limit described above, before data retention is characterized. this means that the flash/ee memory is guaranteed to retain its data for its full-specified retention lifetime every time the flash/ee memory is reprogrammed. it should also be noted that retention lifetime, based on an activation energy of 0.6 v, will derate with t j as shown in figure 11. for example, the data is retained for 100 years at 55 o c operation, but reduces to 15 years at 85 o c operation. beyond such limit, the part must be reprogrammed so that the data can be restored.
rev. 0 AD5233 C17C t j junction temperature c 300 250 0 40 retention years 200 150 100 50 50 60 70 80 90 100 110 adi typical performance at t j = 55 c figure 11. flash/ee memory data retention applications bipolar operation from dual supplies the AD5233 can be operated from dual supplies 2.5 v, which enables control of ground referenced ac signals or bipolar operation. ac signals, as high as v dd /v ss , can be applied directly across terminals aCb with the output taken from terminal w, see figure 12 for a typical circuit connection. 2.5v p-p AD5233 v ss gnd sdi clk ss sclk mosi gnd v dd c 1.25v p-p v dd +2.5v 2.5v cs d = midscale a w b figure 12. bipolar operation from dual supplies gain control compensation digital potentiometer is commonly used in gain control such as the noninverting gain amplifier shown in figure 13. u1 v o r2 100k vi r1 33.2k c1 35pf w ba c2 10pf figure 13. typical noninverting gain amplifier notice that when rdac b terminal parasistic capacitance is con- nected to the op amp noninverting node, it introduces a zero for the 1/ o term with 20 db/dec whereas a typical opamp gbp has C20 db/dec characteristics. a large r2 and finite c1 can cause this zeros frequency to be falling well below the crossover frequency. hence the rate of closure becomes 40 db/dec and the system has a 0 phase margin at the crossover frequency. the output may ring or oscillate if an input is a rectangular pulse or step function. similarly, it is also likely to ring when the switching between two gain values, this is equivalent to a step change at the input. depending on the op amp gbp, reducing the feedback resistor may extend the zeros frequency far enough to overcome the problem, a better approach is to include a compensation capacitor c2 to cancel the effect caused by c1. optimum compensation occurs when r1 c1 = r2 c2. this is not an option because of the variation of r2. as a result, one may use the relationship above and scale c2 as if r2 is at its maximum value. doing so may overcompensate and compromise the performance when r2 is set at low values. on the other hand, it will avoid the ringing or oscillation at the worst case. for critical applications, c2 should be found empirically to suit the need. in general, c2 in the range of few pf to no more than few tenths of pf is usually adequate for the compensation. similarly, there are w and a terminal capacitances connected to the output (not shown), their effect at this node is less significant and the compensation can be avoided in most cases. high voltage operation the digital potentiometer can be placed directly in the feedback or input path of an op amp for gain control, provided that the voltage across terminals aCb, wCa, or wCb does not exceed |5 v|. when high voltage gain is needed, users should set a fixed gain in an op amp operated at high voltage, and let the digital potentiometer control the adjustable input, figure 14 shows a simple implementation. similarly, a compensation capacitor c may be needed to dampen the potential ringing when the digital potentiometer changes steps. this effect is prominent when stray capacitance at the inverting node is augmented by large feedback resistor. in general, a few picofarad capacitor c is adequate to combat the problem. r2r 5v AD5233 a w b 15v v+ v v o 0 to 15v a2 + c figure 14. 15 v voltage span control programmable voltage reference for voltage divider mode operation, figure 15, it is common to buffer the output of the digital potentiometer unless the load is much larger than r wb . not only does the buffer serve the purpose of impedance conversion, but also allows heavier loads to be driven. AD5233 v+ v ad8601 w a1 v in v out gnd ad1582 5v 5v u1 3 a b v o 1 2 figure 15. programmable voltage reference
rev. 0 AD5233 C18C bipolar programmable gain amplifier there are several ways to achieve bipolar gain, figure 16 shows one versatile implementation. digital potentiometer u1 sets the adjustment range; therefore the wiper voltage v w2 can be pro- grammed between v i and Ckv i at a given u2 setting. configuring a 2 as an noninverting amplifier yields a linear transfer function: v v r r d kk o i =+ ? ? ? ? ? ? + () ? ? ? ? ? ? 1 2 164 1 2 C (4) where k is the ratio of r wb /r wa which is set by u1 and d = deci- mal equivalent of the input code. v+ v op2177 AD5233 v o v+ v op2177 AD5233 vi a1 w1 b1 kvi a2 b2 w2 v dd v ss r1 r2 v dd v ss a1 u2 a2 u1 c figure 16. bipolar programmable gain amplifier in the simpler (and much more usual) case, where k = 1, a pair of matched resistors can replace u1. equation 4 simplifies to: v v r r d o i =+ ? ? ? ? ? ? ? ? ? ? ? ? 1 2 1 2 64 1 2 C (5) table xv shows the result of adjusting d , with a2 configured as a unity gain, a gain of 2, and a gain of 10. the result is a bipolar amplifier with linearly programmable gain and 64 step resolution. table xv. result of bipolar gain amplifier dr1 = , r2 = 0 r1 = r2 r2 = 9r1 0 C1 C2 C10 16 C0.5 C1 C5 32 0 0 0 48 0.5 1 5 63 0.968 1.937 9.680 programmable low-pass filter digital potentiometer AD5233 can be used to construct a second order sallen key low-pass filter, figure 17. the design equa- tions are: v v s q s o i o o o = ++ 2 2 2 (6) o rr cc = 1 1212 (7) q rc r c =+ 1 11 1 22 (8) where q = q factor, o = resonant frequency, r1 and r2 = r wb1 and r wb2 respectively. to achieve maximally flat bandwidth where q = 0.707, let c1 be twice the size of c2 and let r1 = r2. users can first select some convenient values for the capacitors, then gang and move r1 and r2 together to adjust C3 db corner frequency. instructions #5, #7, #13, and #15 of the AD5233 make these change simple to implement. a b v i ad8601 +2.5v v o ganged together 2.5v v+ v w r r2 r1 a b w r c 1 c 2 u1 figure 17. sallen key low-pass filter programmable state-variable filter one of the standard circuits used to generate a low-pass, high- pass, or bandpass filter is the state variable active filter. the digital potentiometer AD5233 allows full programmability of the fre- quency, gain, and the q of the filter outputs. figure 18 shows the filter circuit using a 2.5 v virtual ground, which allows a 2.5 vp input and output swing. rdac2 and 3 set the lp, hp, and bp cutoff and center frequencies respectively. rdac2 and rdac3 should be programmed with the same data (as with ganged potentiometers) to maintain the best circuit q. the transfer function of the bandpass filter is: v v a q s s q s bp i o o o o = ++ 2 2 (9) where a o is the gain. for r wb2(d2) = r wb3(d3) , r1 = r2, and c1 = c2: o wb rc = 1 1 2 (10) a r r o wb wa =? 1 1 (11) q r r r r wa wb wb = 4 4 1 1 (12) figure 19 shows the measured filter response at the bandpass output as a function of the rdac2 and rdac3 settings which produce a range of center frequencies from 2 khz to 20 khz. the filter gain response at the bandpass output is shown in figure 20. at a center frequency of 2 khz, the gain is adjusted over C20 db to +20 db range determined by rdac1. circuit q is adjusted by rdac4 and rdac1. the suitable op amps for this application are op4177, ad8604, op279, and ad824.
rev. 0 AD5233 C19C a4 a3 a2 a1 0.01 f 0.01 f rdac3 b lowpass bandpass rdac2 b rdac4 b v in b rdac1 2.5v op279 2 r2 10k r1 10k highpass figure 18. programmable stable variable filter frequency hz 40 20 100 1k 10k 100k 200k amplitude db 0 20 40 60 80 20 20k 16 * figure 19. programmed center frequency bandpass response frequency hz 40 20 100 1k 10k 100k 200k amplitude db 0 20 40 60 80 20 * 2.0k 19.01 figure 20. programmed amplitude bandpass response programmable oscillator in a classic wien-bridge oscillator, figure 21, the wien network (r, r , c, c ) provides positive feedback, while r1 and r2 provide negative feedback. at the resonant frequency, f o , the overall phase shift is zero, and the positive feedback causes the circuit to oscillate. if the op amp is chosen with relatively high gain band- width product, the frequency response of the op amp can be neglected. with r = r , c = c , and r2 = r2a // (r2b + r diode ), the oscillation frequency is: o rc = 1 or f rc o = 1 2 (13) where r is equal r wa such that: r d r ab = 64 64 C (14) at resonance, setting r r 2 1 2 = (15) balances the bridge. in practice, r2/r1 should be set slightly larger than 2 to ensure the oscillation can start. on the other hand, the alternate turn-on of the diodes d 1 and d 2 ensures r2/r1 to be smaller than 2 momentarily and therefore stabilizes the oscillation. once the frequency is set, the oscillation amplitude can be tuned by r2b since: 2 3 2 virbv od d =+ (16) v o , i d , and v d are interdependent variables. with proper selection of r2b, an equilibrium will be reached such that v o converges. r2b can be in series with a discrete resistor to increase the amplitude but the total resistance cannot be too large to saturate the output. in this configuration, r2b can be adjusted from minimum to full scale with amplitude varied from 0.6 v to 0.9 v. using 2.2 nf for c and c , 10 k ? dual digital potentiometer, with r and r set to 8 k ? , 4 k ? , and 700 ? , oscillation occurs at 8.8 khz, 17.6 khz, and 100 khz respectively, see figure 22. in both circuits in figure 17 and 21, the frequency tuning requires that both rdacs to be adjusted to the same settings. since the two channels may be adjusted one at a time, an intermediate state will occur that may not be acceptable for certain applications. of course, the increment/decrement all instructions #5, #7, #13, #15 can be used. different devices can also be used in daisy-chained mode so that parts can be programmed to the same setting simultaneously. +2.5v op1177 v+ v v o 2.5v r2a 2.1k d1 d2 r2b 10k vn r1 1k a b w r = r = r2b = 1/4 AD5233 d1 = d2 = 1n4148 c 2.2nf r 10k ab w vp c 2.2nf r 10k a b w u1 amplitude adjustment frequency adjustment figure 21. programmable oscillator with amplitude control r = 8.06k f = 8.8khz r = 4.05k f = 17.6khz r = 670 f = 102khz 1v/div 1v/div 1v/div figure 22. programmable oscillation
rev. 0 AD5233 C20C programmable voltage source with boosted output for applications require high current adjustment such as laser diode driver or turnable laser, a boosted voltage source can be considered, see figure 23. AD5233 v+ v w a1 v bias 5v a b v s n1 p1 r bias signal c c ld i bias r1 10k a1 = ad8601, ad8605, ad8541 p1 = fdn360p, nds9430 n1 = fdv301n, 2n7002 figure 23. programmable booster voltage source in this circuit, the inverting input of the opamp forces the v bias to be equal to the wiper voltage set by the digital potentiometer. the load current is then delivered by the supply via the p-ch fet p1. the n-ch fet n1 simplifies the opamp driving requirement. a1 needs to be rail-to-rail input type. resistor r1 is needed to prevent p1 for not turning off once it is on. the choice of r1 is a balance between the power loss of this resistor and the output turn off time. n1 can be any general purpose signal fet; on the other- hand, p1 is driven in the saturation state and therefore its power handling must be adequate to dissipate (v s C v bias ) i bias power. this circuit can source maximum of 100 ma at 5 v supply. higher current can be achieved with p1 in larger package. note that a single n-ch fet can replace p1, n1, and r1 altogether. however, the output swing will be limited unless separate power supplies are used. for precision applications, a voltage reference such as adr423, adr292, and ad1584, can be applied at the input of the digital potentiometer. programmable 4 ma-to-20 ma current source a programmable 4 ma-to-20 ma current source can be imple- mented with the circuit shown in figure 24. ref191 is a unique low s upply headroom precision reference that can deliver the 20 ma needed at 2.048 v. the load current is simply the voltage across terminals b-to-w of the digital pot divided by r s . v+ v op1177 u2 vin sleep ref191 gnd vout 3 2 4 6 u1 c1 1 f AD5233 w a b r s 102 r l 100 v l i l +5v 2.048v to v l 5v 0 to (2.048 + v l ) +5v + figure 24. programmable 4-to-20 ma current source the circuit is simple, but beware two things. first, dual supply op amps are ideal because the ground potential of ref191 can swing from C2.048 v at zero-scale to v l at full-scale of the poten- tiometer setting. although the circuit works under single supply, the programmable resolution of system will be reduced. second, the voltage compliance at v l is limited to 2.5 v or equivalently a 125 ? load. should higher voltage compliance be needed, users may consider digital potentiometers ad5260, ad5280, and ad7376. figure 25 shows an alternate circuit for high voltage compliance. programmable bidirectional current source for applications that require bidirectional current control or higher voltage compliance, a howland current pump can be a solution, figure 25. if the resistors are matched, the load cur rent is i ra rb r rb v lw = + ? ? ? ? ? ? 22 1 2 (17) 15v op2177 v+ v +15v + c1 10pf r2 15k r1 150k r2b 50 r l 500 v l r2a 14.95k r1 150k c2 10pf i l op2177 v+ v +15v + 15v a1 AD5233 a b w +2.5v 2.5v a2 figure 25. programmable bidirectional current source r 2b in theory can be made as small as needed to achieve the current needed within a2 output current driving capability. in this circuit op2177 delivers 5 ma in both directions and the voltage compliance approaches 15 v. if there are no c1 and c2, if can be shown that the output impedance becomes z rrbr ra rr r r a r b o = + () ?+ () 12 1 2 12 1 2 2 ' '' (18) z o can be infinite if resistors r1 and r2 match precisely with r1 and r2a + r2b respectively. on the other hand, z o can be negative if the resistors are not matched. as a result, c1 and c2, in the range of 1 f to 10 pf are needed to prevent the oscillation. resistance scaling AD5233 offers 10 k ? , 50 k ? , and 100 k ? nominal resistance. for users who need lower resistance while maintaining the number of adjustment step, they can parallel multiple devices. for example, figure 26 shows a simple scheme of paralleling two AD5233 channels. to adjust half of the resistance linearly per step, users need to program both devices coherently with the same settings. a1 b1 w1 w2 a2 b2 ld v dd figure 26. reduce resistance by half with linear adjustment characteristics in voltage divider mode, a much lower resistance can be achieved by paralleling a discrete resistor as shown in figure 27. the equivalent resistance become: r d rr r wbeq w = () + 64 12 (19)
rev. 0 AD5233 C21C r d rr r waeq w = ? ? ? ? ? ? () + 1 64 12 C (20) r2 r1 b w r2 << r1 a figure 27. lowering the nominal resistance figures 26 and 27 show that the digital potentiometer steps change linearly. on the other hand, log taper adjustment is usually preferred in applications like audio control. figure 28 shows another way of resistance scaling. in this configuration, the smaller the r2 with respect to r1, the more the pseudo log taper characteristic behaves. r1 r2 v o a b w vi figure 28. resistor scaling with pseudo log adjustment characteristics doubling the resolution borrowing from adis patented rdac segmentation technique, we can configure three channels of AD5233 as shown in figure 29 by paralleling a discrete resistor r p (r p = r ab /64) with rdac3, we can double the resolution of AD5233 from 6-bit to 12-bit. we may think of moving rdac1 and rdac2 together forms the coarse 6-bit resolution, then moving rdac3 forms the finer 6-bit resolution. as a result, the effective resolution becomes 12-bit. nevertheless, the precision of this circuit remains only 6-bit accurate and the programming can be complicated. rdac1 a1 b1 va w3 rdac3 a3 b3 rdac2 a2 b2 r p figure 29. doubling AD5233 from 6-bit to 12-bit resistance tolerance, drift, and temperature coefficient mismatch considerations in the rheostate mode operation such as gain control, figure 30, the tolerance mismatch between the digital potentiometer and the discrete resistor can cause repeatability issue among various systems. because of the inherent matching of the silicon process, it is practical to apply the dual or multiple channel device in this type of applications. as such, r1 should be replaced by one of the channels of the digital potentiometer and programmed to a specific value. r2 can be used for the adjustable gain. although it adds cost, this approach minimizes the tolerance and temperature coefficient mismatch between r1 and r2. in addition, this approach also tracks the resistance drift over time. as a result, all these non-ideal parameters become less sensitive to the system variations. ad8601 + vi u1 v o c1 a b w r2 r1 * * replaced with another channel of rdac figure 30. linear gain control with tracking resistance tolerance, and temperature coefficient notice the circuit in figure 31 can also be used to track the toler- ance, temperature coefficient, and drift in this particular application. the characteristic of the transfer function is however a pseudo- logarithmic, rather than a linear, gain function. ad8601 + vi u1 v o c1 ab w r figure 31. nonlinear gain control with tracking resistance tolerance and drift rdac circuit simulation model a b rdac 10k w c w 35pf c b 35pf c a 35pf figure 32. rdac circuit simulation model for rdac = 10 k ? the internal parasitic capacitances and the external load dominate the ac characteristics of the rdacs. configured as a potentiom- eter divider the C3 db bandwidth of the AD5233 (10 k ? resistor) measures 630 khz at half scale. tpc 10 provides the large signal bode plot characteristic. a parasitic simulation model is shown in figure 32. listing i provides a macro-model net list for the 10 k ? rdac: listing i. macro-model net list for rdac .param d=64, rdac=10e3 * .subckt dpot (a,w,b) * ca a 0 35e-12 raw a w {(1-d/64)*rdac+15} cw w 0 35?2 rbw w b {d/64*rdac+15} cb b 0 35e?2 * .ends dpot
rev. 0 AD5233 C22C digital potentiometer family selection guide * number terminal interface nominal resolution power supply part of vrs per voltage data resistance (no. of wiper current number package range (v) control (k ) positions) (i dd ) ( a) packages comments ad5201 1 3, +5.5 3-wire 10, 50 33 40 soic-10 full ac specs, dual supply, pwr-on-reset, low cost ad5220 1 5.5 up/down 10, 50, 100 128 40 pdip, so-8, no rollover, soic-8 pwr-on-reset ad7376 1 15, +28 3-wire 10, 50, 100, 128 100 pdip-14, single 28 v or dual 1000 sol-16, 15 v supply operation tssop-14 ad5200 1 3, +5.5 3-wire 10, 50 256 40 soic-10 full ac specs, dual supply, pwr-on-reset ad8400 1 5.5 3-wire 1, 10, 50, 100 256 5 so-8 full ac specs ad5260 1 5, +15 3-wire 20, 50, 200 256 60 tssop-14 5 v to 15 v or 5 v operation, tc < 50 ppm/ c ad5241 1 3, +5.5 2-wire 10, 100, 256 50 so-14, i 2 c compatible, 1000 tssop-14 tc < 50 ppm/ c ad5231 1 2.75, +5.5 3-wire 10, 50, 100 1024 20 tssop-16 nonvolatile memory, direct program, i/d, 6 db settability ad5222 2 3, +5.5 up/down 10, 50, 100, 128 80 so-14, no rollover, stereo, 1000 tssop-14 pwr-on-reset, tc < 50 ppm/ c ad8402 2 5.5 3-wire 1, 10, 50, 256 5 pdip, so-14, full ac specs, na 100 tssop-14 shutdown current ad5207 2 3, +5.5 3-wire 10, 50, 100 256 40 tssop-14 full ac specs, dual supply, pwr-on-reset, sdo ad5232 2 2.75, +5.5 3-wire 10, 50, 100 256 20 tssop-16 nonvolatile memory, direct program, i/d, 6 db settability ad5235 2 2.75, +5.5 3-wire 25, 250 1024 20 tssop-16 nonvolatile memory, direct program, tc < 50 ppm/ c ad5242 2 3, +5.5 2-wire 10, 100, 256 50 so-16, i 2 c compatible, 1000 tssop-16 tc < 50 ppm/ c ad5262 2 5, +15 3-wire 20, 50, 200 256 60 tssop-16 5 v to 15 v or 5 v operation, tc < 50 ppm/ c ad5203 4 5.5 3-wire 10, 100 64 5 pdip, sol-24, full ac specs, na tssop-24 shutdown current AD5233 4 2.75, +5.5 3-wire 10, 50, 100 64 20 tssop-24 nonvolatile memory, direct program, i/d, 6 db settability ad5204 4 3, +5.5 3-wire 10, 50, 100 256 60 pdip, sol-24, full ac specs, dual tssop-24 supply, pwr-on-reset ad8403 4 5.5 3-wire 1, 10, 50, 100 256 5 pdip, sol-24, full ac specs, na tssop-24 shutdown current ad5206 6 3, +5.5 3-wire 10, 50, 100 256 60 pdip, sol-24, full ac specs, dual tssop-24 supply, pwr-on-reset * for the most current information on digital potentiometers, check the website at: www.analog.com/digitalpotentiometers
rev. 0 AD5233 C23C 24-lead thin surface mount tssop package (ru-24) 24 13 12 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.311 (7.90) 0.303 (7.70) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 outline dimensions dimensions shown in inches and (mm).
C24C c02794C0-3/02(0) printed in u.s.a.

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